Senior RTL Engineer, IO Die and Interconnect IP

The role, as Samsung Semiconductor, Inc. describes it

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Advancing the World’s Technology Together

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team is committed to designing and developing scalable platforms that can effectively handle the computational and memory requirements of these workloads while minimizing energy consumption and maximizing performance. To achieve this goal, we collaborate closely with both hardware and software engineers to identify and address the unique challenges posed by AI/ML workloads and to explore new computing abstractions that can provide a better balance between the hardware and software components of our systems. Additionally, we continuously conduct research and development in emerging technologies and trends across memory, computing, interconnect, and AI/ML, ensuring that our platforms are always equipped to handle the most demanding workloads of the future. By working together as a dedicated and passionate team, we aim to revolutionize the way AI/ML applications are deployed and executed, ultimately contributing to the advancement of AGI in an affordable and sustainable manner. Join us in our passion to shape the future of computing!

Location: Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You’ll Do

• Develop RTL (Verilog/SystemVerilog) for the IO die, integrating UCIe, PCIe, and other high-speed interconnect IP into a cohesive chiplet-based architecture.

• Integrate internal and third-party interconnect IP — UCIe, PCIe, CXL, die-to-die, and NoC — into the IO die, including configuration, glue logic, clock/reset, and interface bridging.

• Modify and customize PCIe and other interconnect IP as needed — controller, PIPE/PHY interface, and configuration logic — to meet die-level requirements and close functional gaps.

• Define and implement die-to-die and chiplet interfaces using UCIe, ensuring protocol compliance and interoperability across chiplets.

• Own the microarchitecture and RTL for IO subsystems such as PCIe/CXL controllers, UCIe adapters, and interconnect fabric bridges.

• Collaborate with verification engineers to develop test plans and debug functional issues at the IP, subsystem, and die level.

• Work with architecture, PHY/SerDes, physical design, and software teams to close requirements across performance, power, area, and interoperability.

• Make design decisions out of a large design trade-off space across performance, power, latency, bandwidth, and cost.

• Develop and automate IP integration and RTL assembly flows using scripting and agentic AI tools and frameworks to improve turnaround time and quality of results.

• Communicate effectively with stakeholders, including users, partners, and management, to ensure that the die is delivered on time and within budget.

• Complete other responsibilities as assigned.

What You Bring

• Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD's with 0+ years of industry experience.

• Strong background in microarchitecture and RTL design for complex SoC and die integration.

• 5+ years of experience in RTL developmen

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