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Senior HSIO Digital Design Engineer

Samsung Semiconductor, Inc. · San Jose, CA · posted 10 days ago

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91
Certified filings · by Samsung Semiconductor, Inc., FY2026 Q2
$152,506
Median filed wage · for “Senior Engineer” · 10 filings

Source: US DOL Office of Foreign Labor Certification, LCA disclosure data, FY2026 Q2. Government data is published roughly one quarter in arrears.

This advert was matched to Senior Engineer, a job title Samsung Semiconductor, Inc. has itself sponsored.

The figure above is not this job’s salary. It is what Samsung Semiconductor, Inc. reported to the US Department of Labor for the closest role it has sponsored. A filing history means this employer has sponsored before — it is not a promise that this opening carries sponsorship, and not an offer of pay. Check the advert and ask the employer.

See every role Samsung Semiconductor, Inc. has sponsored, and what it paid →

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The role, as Samsung Semiconductor, Inc. describes it

Please Note:

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Advancing the World’s Technology Together

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

Please Note:

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Advancing the World’s Technology Together

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

Samsung’s San Jose Location Group in US was established in October 2012 to develop industry leading location technology IP for mobile and wearable applications. The group develops premium tier products and drives the technology for next generation products. The team is responsible for all aspects of building products from concept (algorithm design) to productization – i.e., architecture definition, silicon design, algorithm and software development, platform integration, performance optimization, test and commercialization. The Location Group is an integral part of the broader SoC organization responsible for Exynos line of SoC products that cover all IPs including Application Processor, Communication Processor, Connectivity, GPU, NPU etc. and hence enables us to develop highly integrated products and optimize our solution to be the best in class.

This team is focused on next-generation HSIO (High-Speed I/O) design for Samsung’s AI production platforms. Ideal candidates will have 3+ years of industry experience specializing in digital design for die-to-die(chiplet) interfaces or similar high-speed I/O technologies.

Candidates are expected to have a strong understanding of the end-to-end digital design flow and the ability to collaborate effectively with system and analog teams.

Location: Working onsite at our San Jose headquarters

What You’ll Do

  • BS in Electrical Engineering with 5+ Years of experience, MS in Electrical Engineering with 3+ years of experience or PhD in Electrical Engineering
  • Hands-on experience in High-Speed I/O PHY IP development, with expertise in one or more of the following areas:
  • Strong understanding of high-speed serial interconnect protocols and associated design trade-offs
  • Solid understanding of how analog and mixed-signal design and verification impact digital-on-top development flows
  • Knowledge of Signal Integrity (SI) and Power Integrity (PI) modeling for High-Speed I/O designs

What You Bring

  • Understanding of SoC protocols including AXI/CHI/CXS.B/CXL/PCIE/UA-Link
  • Familiarity with HSIO PHY layers protocols and architectures

What We Offer The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities

Read the full advert and apply on Samsung Semiconductor, Inc.’s site →

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